1. Field of the Invention
The invention is generally related to lithography exposure systems and methods for wafer and chip manufacture. More specifically, the invention is directed to a reduction projection imaging system wherein X-Y movements of the reticle used to pattern the fields on the wafer or chip are eliminated.
2. Description of the Prior Art
While current optical lithography is now capable of patterning integrated circuits below 0.5 microns, the wavelength of the exposing light eventually will limit the application of this technology. The wavelength not only limits resolution, but, most importantly, the depth of focus, requiring complex "tricks" to extend it. Thus, X-ray, electron, and/or ion beam lithography techniques are likely to become the method of choice for producing feature sizes approaching 0.1 microns or smaller.
Photo-optical reduction projection systems are the mainstream tools for integrated circuit lithography. They are capable of exposing the entire area of one or more integrated circuit chips at a time. Analogous systems using particle beams have not proven feasible to this date. A combination, however, of reduction projection optics and established technology of probe-forming electron beam lithography systems appears to be a feasible approach. For example, a beam with defined size is scanned across a reticle containing the enlarged replica of the circuit pattern to be delineated on the substrate (wafer), thereby sequentially illuminating portions of the pattern, which then are demagnified by the electron optical elements (lenses) of the system and projected onto the wafer. The Japanese patent application JP 61-283121 to Nippon Telegraph & Telephone company, which is incorporated by reference, describes fundamentals of such a system, referred to as "conventional reduction projection systems" hereafter. In addition to the beam scanning, these systems require the step-wise or continuous placement of reticle and wafer in synchronism "under the beam", i.e., within the scanning range of the beam, since this range is in general insufficiently large to cover the entire chip area. Often, the mechanical motion follows a serpentine path, covering the chip area in parallel stripes of limited width.
U.S. Pat. No. 5,263,073 to Feldman, which is incorporated by reference, describes traditional serpentine and step-and-scan stage motions employed in reduction projection lithography systems. Conventional reduction projection lithography systems place great demands on the mechanical and electrical systems, which provide the stage movements of the reticle and the substrate in order to achieve the throughput necessary for profitable semiconductor chip and wafer manufacturing. The reticle stage system is more severely stressed than the substrate stage system, because the speed of the reticle stage movements must be higher than that of the substrate stage by the optical reduction factor. Thus, scanning a rectilinear array of subfields, which compose a chip pattern, at high speeds (e.g., 400-500 mm/s) with multiple acceleration and deceleration operations places severe demands on the mechanical handling system in terms of system stability, vibration control, synchronism and accuracy of reticle and wafer stage motions, reticle clamping, and overall complexity, and these demands result in increased costs associated with the reticle stage and control system.
Japanese Patent abstract 59-189268 to Hitachi Ltd. describes a system that improves throughput and reduces costs, wherein the drawing region of the reticle is divided into four segments with two parts oriented vertically and two parts oriented horizontally. In operation, the pattern is drawn on the substrate by drawing one of the four segments, then rotating the stage 90 degrees at the end of the segment to draw the next segment, and so on. This system essentially is a step-and-scan approach which would still suffer some of the problems related to mechanical movement control discussed above. In addition, the Hitachi system may be limited for use in exposing small chips on the order of 5 mm since the pattern is only split into four segments.